Instruction set architecture

Results: 1722



#Item
11Computing / Computer architecture / Embedded microprocessors / Electronics / ESi-RISC / EnSilica / Instruction set architectures / Soft microprocessor / Nios II

eSi-3200 – 32-bit, low-cost & low-power CPU EnSilica’s eSi-3200 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs with on-chip memories. The eSi-3

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Source URL: www.avant-tek.com

Language: English - Date: 2014-10-14 01:56:26
12Computer architecture / Advanced RISC Computing / MIPS Technologies / Computer engineering / Computing / MIPS instruction set / Fabless semiconductor companies / Imagination Technologies / Chipset / MIPS / 64-bit computing

New H.265 hybrid set-top box chipset from ALi Corp. gets a boost with MIPS CPUs London, UK & Taipei, Taiwan – June 23, 2016 – Imagination Technologies (IMG.L) announces that ALi Corporation, a leading set-top box (ST

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Source URL: www.ali.com.tw

Language: English - Date: 2016-06-22 21:06:46
13Computer architecture / Computing / Computer engineering / Compiler optimizations / Software pipelining / Optimizing compiler / UltraSPARC / Loop unrolling / SPARC / Visual Instruction Set / Microarchitecture / 64-bit computing

Copyright 1999 IEEE. Published in the Proceedings of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, October, Pacific Grove, CA, USA. Real-Time High-Throughput Sonar Beamforming Kernel

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Source URL: bevo.duckdns.org

Language: English - Date: 2010-02-15 01:30:13
14Computing / Computer architecture / Computer hardware / Central processing unit / Parallel computing / Microprocessors / Stack machines / Transputer / Supercomputers / Occam / Inmos / Instruction set

Dissertation Type: enterprise DEPARTMENT OF COMPUTER SCIENCE OpenTransputer: reinventing a parallel machine from the past David Keller, Andres Amaya Garcia

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Source URL: wordpress-transputeriot.rhcloud.com

Language: English - Date: 2015-06-25 15:49:37
15Computing / Central processing unit / Computer engineering / Computer architecture / Instruction set / Portable Document Format / Processor register

BOOKS ABOUT R 540X INSTRUCTIONS Cityhalllosangeles.com R 540X INSTRUCTIONS

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Source URL: r.cityhalllosangeles.com

Language: English - Date: 2015-03-05 01:55:22
16Computing / Computer architecture / Computer engineering / Instruction set architectures / Computer memory / Assembly languages / Stack / Processor register / Endianness / Comparison of instruction set architectures / 16-bit / Pointer

4stack Processor’s User Manual Bernd Paysan 25th April 2000 2

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Source URL: bernd-paysan.de

Language: English - Date: 2000-04-25 15:51:49
17Computing / Broadcast engineering / Digital radio / Digital television / Multiplexing / 4-bit / 64-bit computing / Computer architecture / Data / Digital media / Instruction set architectures / Bit array

Description of the VDIF Extended Data Version 4: Multiplexed VDIF Data Validity Walter Brisken 07 Jan

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Source URL: www.vlbi.org

Language: English - Date: 2016-01-15 21:14:35
18Computer architecture / Computing / Computer engineering / Central processing unit / Static timing analysis / Bubble / Parallel computing / Instruction set / Microarchitecture / Clock signal / Optimizing compiler / ARM architecture

IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. XX, Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

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Source URL: mesl.ucsd.edu

Language: English - Date: 2014-04-29 20:45:28
19Software / Computer architecture / Computing / Linux distributions / Instruction set architectures / X86 architecture / X86-64 / SUSE Linux Enterprise Server / Oracle Developer Studio / IA-64 / Solaris / Oracle Database

HydraExpress® 4.9 Supported Platforms OS AIX IBM AIX 6.1 (TL6100IBM AIX 7.2

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Source URL: docs.roguewave.com

Language: English - Date: 2016-07-06 17:40:46
20Computer architecture / Central processing unit / Computing / Computer engineering / Arithmetic logic unit / Datapath / 1-bit architecture / ANTIC / Instruction set / Register file / Classic RISC pipeline

cs281: Computer Systems CPUlab – ALU and Datapath Assigned: Oct. 30, Due: Nov. 8 at 11:59 pm The objective of this exercise is twofold – to complete a combinational circuit for an ALU that

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Source URL: personal.denison.edu

Language: English - Date: 2015-11-10 08:26:31
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